ESD5302N will semiconductor ltd. 1 revision 1.5, 2014/10/16 esd 5302 n 2 - line s , un i - d irectional, ultra - low capacitance trans ient voltage suppressors descriptions the esd5302 n is a n ultra - low capacitance tvs (tran sient voltage suppressor) array designed to protect high speed data interfaces. it has been specificall y designed to protect sensitive electronic components which are connected to data and transmission lines from over - stress caused by esd (e lectro s tatic d ischarge ) . the esd5302 n incorporates two pair s of ultra - low capacitance steering diodes plus a tvs diod e. the esd530 2 n may be used to provide esd protection up to 2 0 k v (contact and air discharge ) according to iec61000 - 4 - 2 , and withstand peak pulse current up to 4 a ( 8/20 s ) according to iec61000 - 4 - 5. the esd530 2 n is available in dfn1006 - 3 l package. standard products are pb - free and halogen - free. features ? stand - off voltage: 5 v max. ? transient protection for each line according to iec61000 - 4 - 2 (esd) : 20 k v ( contact and air discharge ) iec61000 - 4 - 4 (eft): 40a (5/50ns ) iec61000 - 4 - 5 (surge): 4 a (8/20 s) ? ultra - low capacitance: c j = 0.4 pf typ. ? ultra - low leakage current: i r <1 na typ. ? l ow clamping voltage : v cl = 1 7. 5 v @ i pp = 16a (tlp) ? solid - state silico n technology applications ? usb 2.0 and usb 3.0 ? hdmi 1.3 and hdmi 1.4 ? sata and esata ? dvi ? ieee 1394 ? pci express ? porta ble electronics and notebooks h ttp //: www. sh - willsemi.com dfn1006 - 3 l (bottom v iew) circuit d iagram 3 = device code * = month code ( a~z) marking (top view) order i nformation device package shipping esd530 2 n - 3 /tr dfn1006 - 3 l 10 000/tape&reel 2 1 3 1 3 2 3 *
ESD5302N will semiconductor ltd. 2 revision 1.5, 2014/10/16 absolute m aximum r ating s electrical characteristics ( t a = 25 o c, unless otherwise noted ) notes: 1) tlp parameter: z 0 = 50 , t p = 100ns, t r = 2n s, averaging window from 60ns to 80ns. r dyn is calculated from 4a to 16a. 2) non - repetitive current pulse, according to iec61000-4 -5. parameter symbol rating unit peak pulse power ( t p = 8/20 parameter symbol condition min. typ. max. unit rever se maximum working voltage v rwm 5.0 v reverse leakage current i r v rwm = 5v <1 100 n a reverse breakdown voltage v br i t = 1ma 7.0 8.0 9.0 v forward voltage v f i t = 1 0ma 0.6 0.9 1.2 v clamping voltage 1) v cl i pp = 16a, t p = 100ns 1 7.5 v dynamic resis tance 1) r dyn 0. 53 2 ) v cl i pp = 1a, t p = 8/20s = 8/20s
ESD5302N will semiconductor ltd. 3 revision 1.5, 2014/10/16 typical characteristics ( t a = 25 o c, unless otherwise noted ) 8/20 s w aveform per iec61000 - 4 - 5 clamping voltage vs. peak pulse current non - repetitive peak pulse p ower vs. pulse time contact discharge current waveform per iec61000 - 4 - 2 capacitance vs. reveres voltage power derating vs. ambient t emperature 0 1 2 3 4 5 0.20 0.25 0.30 0.35 0.40 0.45 0.50 between pin1 and pin2 pin1 or 2 to pin3 f = 1mhz c j - junction capacitance (pf) v r - reverse voltage (v) 1 10 100 1000 1 10 100 1000 peak pulse power (w) pulse time (
ESD5302N will semiconductor ltd. 4 revision 1.5, 2014/10/16 typical characteristics ( t a = 25 o c, unless otherwise noted ) esd clamping ( +8kv contact discharge per iec61000 - 4 - 2) tlp measurement esd clamping ( - 8kv contact discharge per iec61000 - 4 - 2 ) 0 2 4 6 8 10 12 14 16 18 20 22 -2 0 2 4 6 8 10 12 14 16 18 20 z 0 = 50 ? t r = 2ns t p = 100ns tlp current (a) tlp voltage (v)
ESD5302N will semiconductor ltd. 5 revision 1.5, 2014/10/16 application information the ESD5302N is designed to protect two high speed line against esd. fig1 is shown the connection and fig2 is shown pc b layout guide for usb interface esd protection fig1 fig2 vbus dm dp id gnd vbus dm dp id gnd
ESD5302N will semiconductor ltd. 6 revision 1.5, 2014/10/16 package outline dimensions dfn 1006- 3 l top view bottom view side view recommend l and p attern (unit: mm) symbol dimensions in millimeter min. typ. max. a 0.4 0 - 0.5 0 a1 0.00 - 0.05 a3 0.125 re f d 0.95 1.00 1.05 e 0.55 0.60 0.65 b1 0.10 0.15 0.20 b2 0.20 0.25 0.30 l1 0.20 0.30 0.40 l 2 0.40 0.50 0.60 e1 0.35 0 bsc e2 0.675 bsc note s : t his recommended land patte rn is for reference purposes only. please consult your manufacturing group to ensure your pcb design guidelines are met. 0.45 0.70 0.45 0.25 0.25 0.20
ESD5302N will semiconductor ltd. 7 revision 1.5, 2014/10/16 tape and reel specification symbol dimensions in millimeter min. typ. max. a0 0. 65 0.70 0.75 b0 1.10 1.15 1.20 k0 0.50 0.55 0.60 f 3 .45 3.50 3.55 p1 1.90 2.00 2.10 w 7.90 8.00 8.10
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